R_(DSon) of a power LDMOS in the triode region of operation is determined by the dimensions and doping concentrations of its channel and drift regions. For a non-self-aligned LDMOS, one end of the drift region is not self aligned to the gate. The channel length of the device could be affected by many process variations such as photo CD, overlay performance, etch CD, etc. During the development of SMOS7LV~(TM) technology at Motorola, it was found that the R_(DSon) variation of a non-self aligned power LDMOS was larger than the specified 8% (1σ). Analysis of the R_(DSon) variation showed that the primary cause was poor overlay performance. An optimized alignment scheme reduced the variation from ～12% to <3%.
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