Back-Gate Effect on $R_{mathrm {{mathrm{{scriptscriptstyle ON}},sp}}}$ and BV for Thin Layer SOI Field p-Channel LDMOS

摘要

The Backgate (BG) effect on specific ON-resistance ( and breakdown voltage (BV) for the thin layer Silicon On Insulator (SOI) field p-channel lateral diffusion MOS (pLDMOS) are investigated in this paper. BG-induced dual conduction mode for the thin layer SOI field pLDMOS is revealed, which includes drift and accumulation conduction. Hole accumulation layer induced by BG voltage ( provides extra charges, resulting in a reduction. An expression of equivalent is given to describe the dependence of on . Simultaneously, impacts strongly on BV, inducing three breakdown mechanisms: surface breakdown, bulk breakdown, and punchthrough breakdown. For surface breakdown, a positive linear dependence of BVs on is given with consideration to multiple field plates (MFP). BV of −366 V and of mm