Today and for the foreseeable future, the most critical element in the conception of new products is to identify the right technologies for the right product at the right time. The development of new miniaturized electronic components and modules is the key to success. Main trend for single die packages is thickness reduction that is necessary to fit the packages into thin products. As first level interconnect, flip chip is gaining popularity for high I/O count packages and for packages that demand high electrical performance. Recently, Intel has shown plans to industrialize a first level interconnection method in which the die is embedded in the substrate by thin film technology. One of the advantages is the realization of ultra-thin packages. Compared to other package types, the number of CSPs grows fastest. Wafer-level CSPs offer the highest degree of miniaturization. Leadframe based CSPs are reliable packages that can be manufactured using standard technologies. The largest flip chip applications are chip on foil (for Display Drivers) and flip chip in package. Flip chip on board is used only sporadically due to the requirement for expensive high-definition boards and the need for underfilling. No flow underfill might help to remove the second bottleneck. Because of smaller pitch capabilities and lower cost, chip on foil will replace tape carrier packages in the Display Driver business. Interconnect pitch is expected to reach 25-30 μm in 2005. Modules (system in package) are used for low-cost high-volume products for which a short time-to-market is essential. With modules, this can be realized because new functions are developed by combining and mixing existing die designs. Another solution to provide a functional block is a system on a chip (SOC). As they are more expensive and have a long time-to-market, they are typically used for function integration in high-performance systems. The move towards lead-free soldering processes and packages requires the adaptation of MSL test procedures. In general the MSL level rises 1 or 2 levels compared to standard PbSn soldering. Pure Sn plating is the preferred lead-free plating alternative. The only concern is the occurrence of whiskers. It has been proven that, when the plating layer has a certain thickness, no whiskering occurs. A second environmental issue is the use of green molding compounds that also withstand the higher reflow temperature for lead-free soldering.
展开▼
