Multi-slope analog-to-digital converters modeling based on VHDL-AMS

摘要

This paper attempts to validate the conversion algorithm of a multi-slope self-calibrated analog-to-digital converter by means of VHDL-AMS static test has been performed for a 8-b multi-slope self-calibrated A/D converter. Obtained results in terms of linearity errors (DNL and INL) proved the efficiency of the converter in several applications.