Charge and Interface Traps in 1-Octadecene Monolayers on Silicon as a Function of Silicon Pretreatment and Deposition Regime

摘要

The electrical properties of 1-octadecene (C{sub}nH{sub}(2n), n=18) monolayers deposed onto the oxide-free silicon surface were analyzed as a function of surface pretreatment (hydrogen- or iodine-terminated silicon surface) and layer deposition regime (a thermally or photo-activated process). Two types of traps (for electrons and holes) were found to exist in the monolayers. The density of these traps is shown to depend on the orientation of the Si substrate, on H- or I-termination of the surface, on the illumination intensity during photo-activated deposition, and on the duration of thermally activated deposition. The possibility to introduce, in a controllable manner, either hole or electron traps into the 1-octadecene monolayers provides a potential in managing the conductivity of thin silicon layers by producing at the surface either a near flat band situation or accumulation conditions.