FPGA-Oriented Design of an FDTD Accelerator Based on Overlapped Tiling

摘要

In this paper, we introduce the overlapped tiling to designing an FPGA-based FDTD accelerator by using an OpenCL compiler. The OpenCL compiler for FPGA enables us to reduce the design time of the FPGA-based accelerators. However, the FPGA-based accelerator generated from common OpenCL codes cannot accelerate the processing efficiently in some applications such as an FDTD computation. To accelerate the FDTD computation, global memory access can be reduced by storing the small partition of the electronic and magnetic fields with enclosed areas into the local memory. According to the result of the implementation of the FDTD accelerator on the FPGA, the processing speed with overlapped tiling is far faster than that without overlapped tiling. Moreover, the processing speed is faster than a GPU when the number of grids is small.