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FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling

机译：基于FPGA的层间流水线加速器，用于滤波器的重量平衡的稀疏完全卷积网络，具有重叠的平铺

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Masayuki Shimoda; Youki Sada; Hiroki Nakahara;
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1. FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling [J] . Shimoda Masayuki, Sada Youki, Nakahara Hiroki Journal of signal processing systems for signal, image, and video technology . 2021,第5期

机译：基于FPGA的层间流水线加速器，用于滤波器的重量平衡的稀疏完全卷积网络，具有重叠的百帘
2. SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators [J] . Masayuki SHIMODA, Youki SADA, Ryosuke KURAMOCHI, IEICE transactions on information and systems . 2020,第12期

机译：Sentei：通过蒸馏到有效的稀疏卷积神经网络加速器的滤波器 - 明智的修剪
3. WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm [J] . Wang Xuan, Wang Chao, Cao Jing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2020,第11期

机译：WINONN：使用稀疏Winograd算法优化基于FPGA的卷积神经网络加速器
4. Tile-Based Architecture Exploration for Convolutional Accelerators in Deep Neural Networks [C] . Yang-Tsai Chen, Yu-Xiang Yen, Chun-Tse Chen, IEEE International Conference on Artificial Intelligence Circuits and Systems . 2021

机译：深神经网络卷积加速器的基于瓷砖架构探索
5. FPGA-based Accelerators for Convolutional Neural Networks on Embedded Devices [D] . Perera Miro, Jordi. 2020

机译：基于FPGA的嵌入式设备卷积神经网络的加速器
6. Sparse Convolutional Neural Networks for Genome-Wide Prediction [O] . Patrik Waldmann, Christina Pfeiffer, Gábor Mészáros 2020

机译：全基因组预测的稀疏卷积神经网络
7. NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps [O] . Aimar, Alessandro, Mostafa, Hesham, Calabrese, Enrico, 2017

机译：NullHop：一种基于FpGa的灵活卷积神经网络加速器特征映射的稀疏表示

FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling

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