Comparative Study of p{sup}+/n{sup}+ gate Modified Saddle MOSFET and p{sup}+/n{sup}+ gate Bulk FinFETs for Sub-50nm DRAM Cell Transistors

摘要

DRAM market in these days strongly demands much faster random access, higher density and longer retention time. To meet these demands, cell array transistors have to be improved to get higher scalability, higher on-current (I{sub}(on)) and lower off-current (I{sub}(off)). A reasonable approach to meet these needs is to adopt 3-dimensional (3-D) cell transistors such as RCATs[1], FinFETs[2], and Saddle MOSFETs[3]. Among 3-D devices ever reported, suitable device structures for sub-50nm DRAM cell application would be FinFETs[2] and Saddle MOSFETs[3]. In the scaling-down of these devices, body width becomes narrow, which results in threshold voltage (V{sub}(th)) lowering for n{sup}+ poly-gate and resultant I{sub}(off) increase. To solve the leakage problem, p{sup}+-poly gate can be adopted, but I{sub}(off) increases due to GIDL. In this work, we propose p{sup}+/n{sup}+ gate and apply it to modified Saddle MOSFET and bulk FinFET to solve the problems mentioned above. We compare both devices in terms of scalability and show electric field profiles. The device characteristics are studied by using 3-D device simulator [4].