Nucleation,Growth and Post Deposition Annealing of Atomic Layer Deposited (ALD) High-K Gate Dielectric Layers

摘要

High-K gate dielectrics will be required when the SiO_2 gate dielectric thickness decreases to -1.3 nm,if CMOS scaling is to continue,since leakage currents will be excessively high.Low leakage,low power applications,such as for portable devices,might necessitate high-K implementation for thicker EOT's,perhaps < 2.0 nm.