HPC GPS BASED AUTONOMOUS NAVIGATION SYSTEM FOR FUTURE GENERATIONS OF SATELLITES

摘要

This paper elaborates on the development of a space born autonomous navigation system utilising the advanced Global Positioning System (GPS) and High Performance Computing (HPC) technology for future generations of satellite systems. GPS is a device integrated into the satellite system to sense spacecraft trajectory and attitude, measure the relative distance between space vehicles, deliver precise time synchronisation to spacecraft electronics, and sound the atmosphere. However, the advances in GPS technology are not sychronised with the current capability of a standard spacecraft system to handle all the measurements and provide on-board processing capacity to use these measurements for autonomous navigation. Current spacecraft systems provide very limited on-board computing capability, and therefore these satellites rely on other devices to provide information about the spacecraft position such as star cameras and some times require ground processing of data to give instructions on appropriate positions of the satellite. HPC systems consist of reconfigurable logic circuits added to a conventional processor to generate a powerful system for handling intensive computing tasks. Reconfigurable Computing Technology (RCT) using Field Programmable Gate Arrays (FPGAs) represents a flexible computing platform where both the hardware and the software can be programmed on an application by application basis. This emerging technology is very promising for a lot of applications, especially satellite systems. This paper investigates the deployment of HPC in the context of real-time reactive computer system on-board the spacecraft in conjunction with the GPS to implement the autonomous navigation system. In particular, the paper introduces the use of a reconfigurable computer for position and velocity computations of the spacecraft efficiently, with a focus on cost-effective implementation of precise orbit determination and control algorithms on FPGAs. Experimental testbeds for this research are also presented.