Low thermal budget processing for Silicon nitride

摘要

The relentless pursuit of faster chips and higher packing densities for increased functionality are the 2 main . motivators behind ever-decreasing device dimensions. However, the scaling of MOSFETs into the deep submicron regime requires very shallow and abrupt doping profiles in the active region. For example, as we scale down from 0.18um to 0.10um technologies, the junction depth for source/drain implants will decrease from 50nm to 35nm respectively. Consequently, ultra-low energy implantation is being widely pursued for shallow junctions for advanced device technologies. On the other hand, the high thermal budget, i.e. higher process temperatures and long times at process temperatures, of subsequent thermal processing causes dopant redistribution and distorts the desired doping profiles. This redistribution has a direct impact on the device performance, leading to threshold voltage shifts and increased source/drain junction capacitance amongst others.