A demonstration of co-design and co-verification in a synchronous language

摘要

This paper illustrates how the synchronous programming language Esterel [3] can be used to design and verify both hardware and software. Also illustrates that power of combining these two complementary technologies for the design and verification of embedded systems. Finally we show how the Esterel technique fits into a conventional system level design flow based on Xilinx's Virtex-II PRO FPGA and present several case studies and actual demonstration of a complete system from concept to implementation.