A dual salicide process scalable to sub-0.25-/spl mu/m CMOS technologies

摘要

A novel salicide process is presented which allows for independent silicidation of source/drain areas and polysilicon gates, thus making it possible to achieve ultra-shallow junction formation with very low gate sheet resistance (R/sub s/) for sub-0.25 /spl mu/m CMOS device fabrication. Titanium was used to demonstrate this process in a 0.25 /spl mu/m technology, yielding fully functional transistors with gate R/sub s/2 /spl Omega//sq.