Tradeoffs in chip and substrate complexity and cost for field progammable multichip modules -- part II: the clique architecture

摘要

Field programmable MCMs (FPMCMs) can be used to improve the cost-effectiveness of large logic emulation and reconfigurable computing systems. In this paper, we consider the cost-performance tradeoff for the Chque architecture for FPMCMs. Wepresent a simple model for determining the most cost-effective Clique architecture with a given number of usable gates, and use this model to characterize the Clique architecture against single-chip FPLDs and the more common bipartite architecture. Wefind that that cost-effective implementations of Clique require area-IO FPLDs which are specially designed for FPMCM. With these special measures, Clique FPMCMs can reach about 3 times the logic capacity of the largest single chips.