Placement of multiple dies on an MCM or hi9hperformance VLSI substrate is a non-trivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-ob5ective optimization. Unfortunately, the exact physicalattributes of a design are not known in the placement step until the entire design process is carried out. When the performance issues are considered, crosstalk noise constraints in the form of net separation and via constraint become important. In thispaper, for better performance and wirability estimation during placement for MCMs, several performance constraints are taken into account simultaneously. A graph-based wirability estimation along with the Genetic placement optimization technique isproposed to minimize crosstalk, crossings, wire length and the number of layers. Our work is significant since it is the first attempt at bringing the crosstalk and other performance issues into the placement domain.
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