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Dependence of resistivity in evaporated cadmium selenide thin films on preparation conditions and temperature

机译:电阻率在蒸发镉硒化型薄膜中的依赖性制备条件和温度

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The lateral resistivity of evaporated CdSe thin films has been measured using the van der Pauw technique. Measurements were performed as a function of the film thickness, the deposition rate and the substrate temperature during deposition. Such measurements are useful in the context of the development of inexpensive solar cells based on this material. In contrast to some other cadmium compounds the mean resistivity appeared to increase with increasing thickness, prior to a rapid decrease at a thickness above about 1 micrometer. This effect is thought to be related to the varying composition of the evaporating CdSe charge during the course of the evaporation process. Films deposited at a substrate temperature of 200 degrees Celsius (473 K) showed a rapid increase in resistivity from below 10$+2$/ approximately ega m to above 1 approximately ega m as the deposition rate increased up to approximately 0.5 nm s$+$MIN@1$/, while for rates above this value and up to 3 nm s$+$MIN@1$/ the resistivity remained essentially constant. This behavior is thought to be related to a decrease in mobility and/or free carrier concentration resulting respectively from increasing grain boundary scattering and trapping effects, as a result of a decrease in the mean grain size with increasing deposition rate. Resistivity was strongly dependent on the substrate temperature during deposition, showing a moderate increase with increasing temperature up to about 75 degrees Celsius (approximately equal to 350 K), followed by a very rapid increase of typically three decades up to 100 degrees Celsius (373 K), above which the value stabilized at an essentially constant value. Previous work has identified the origin of lower resistivity CdSe films as being the result of an excess of Cd ions while stoichiometric films are normally of higher resistivity. The present results indicate that a substrate temperature in excess of 100 degrees Celsius (approximately equal to 400 K) is necessary for the deposition of stoichiometric films. As expected conductivity was thermally activated and the resistivity decreased with increasing temperature. Samples prepared at a substrate temperature of 200 degrees Celsius (473 K) showed activation energies of approximately 0.02 eV and 0.14 eV at lower and higher temperatures, respectively. The low temperature behavior is consistent with conduction via a hopping mechanism, while the latter is appropriate for thermal excitation over inter-crystalline potential barriers as proposed by Petritz and previously observed in CdS films.
机译:使用VAN DER PAUW技术测量蒸发CDSE薄膜的横向电阻率。在沉积期间作为膜厚度,沉积速率和衬底温度的函数进行测量。这种测量在基于该材料的廉价太阳能电池的发展的背景下是有用的。与其他一些镉化合物相反,平均电阻率随着厚度的增加而似乎增加,在高于约1微米的厚度的快速降低之前。认为这种效果与在蒸发过程过程中蒸发CDSE电荷的变化组成有关。沉积在200摄氏度(473k)的基板温度下沉积的薄膜显示出在10 $ + 2 $ /大约1至高于1的电阻率的快速增加,因为沉积速率增加到大约0.5nm的$ + $ min @ 1 $ /,虽然该值高于此值,最多3 nm s $ + $ min @ 1 $ /电阻率仍然是恒定的。由于沉积率的平均晶粒尺寸的降低,这种行为被认为分别从增加晶粒边界散射和捕获效果产生的迁移率和/或自由载流量的降低相关。电阻率强烈依赖于沉积期间的基材温度,显示温度升高至约75摄氏度(大约等于350 k)的中等增加,然后典型三十年的速度增加到100摄氏度(373k ),高于该值以基本恒定的值稳定。以前的工作已经确定了较低电阻率CDSE薄膜的起源,作为过量的CD离子的结果,而化学计量膜通常具有更高的电阻率。本结果表明,底物温度超过100摄氏度(大约等于400 k)对于沉积化学计量膜是必要的。随着预期的电导率被热激活,并且电阻率随温度的增加而降低。在200摄氏度(473k)的底物温度下制备的样品在较低且较高温度下分别显示出约0.02eV和0.14eV的活化能量。低温行为与通过跳频机构的传导一致,而后者适合于通过Petritz提出的晶体间电位屏障的热激发,并且在CD膜中先前观察到。

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