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Dependence of resistivity in evaporated cadmium selenide thin films on preparation conditions and temperature

机译:蒸发的硒化镉薄膜的电阻率与制备条件和温度的关系

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Abstract: The lateral resistivity of evaporated CdSe thin films has been measured using the van der Pauw technique. Measurements were performed as a function of the film thickness, the deposition rate and the substrate temperature during deposition. Such measurements are useful in the context of the development of inexpensive solar cells based on this material. In contrast to some other cadmium compounds the mean resistivity appeared to increase with increasing thickness, prior to a rapid decrease at a thickness above about 1 micrometer. This effect is thought to be related to the varying composition of the evaporating CdSe charge during the course of the evaporation process. Films deposited at a substrate temperature of 200 degrees Celsius (473 K) showed a rapid increase in resistivity from below 10$+2$/ approximately ega m to above 1 approximately ega m as the deposition rate increased up to approximately 0.5 nm s$+$MIN@1$/, while for rates above this value and up to 3 nm s$+$MIN@1$/ the resistivity remained essentially constant. This behavior is thought to be related to a decrease in mobility and/or free carrier concentration resulting respectively from increasing grain boundary scattering and trapping effects, as a result of a decrease in the mean grain size with increasing deposition rate. Resistivity was strongly dependent on the substrate temperature during deposition, showing a moderate increase with increasing temperature up to about 75 degrees Celsius (approximately equal to 350 K), followed by a very rapid increase of typically three decades up to 100 degrees Celsius (373 K), above which the value stabilized at an essentially constant value. Previous work has identified the origin of lower resistivity CdSe films as being the result of an excess of Cd ions while stoichiometric films are normally of higher resistivity. The present results indicate that a substrate temperature in excess of 100 degrees Celsius (approximately equal to 400 K) is necessary for the deposition of stoichiometric films. As expected conductivity was thermally activated and the resistivity decreased with increasing temperature. Samples prepared at a substrate temperature of 200 degrees Celsius (473 K) showed activation energies of approximately 0.02 eV and 0.14 eV at lower and higher temperatures, respectively. The low temperature behavior is consistent with conduction via a hopping mechanism, while the latter is appropriate for thermal excitation over inter-crystalline potential barriers as proposed by Petritz and previously observed in CdS films. !25
机译:摘要:已使用范德堡技术测量了蒸发的CdSe薄膜的横向电阻率。根据膜厚度,沉积速率和沉积期间的基板温度进行测量。在基于这种材料的廉价太阳能电池的开发中,这种测量是有用的。与其他一些镉化合物相比,平均电阻率似乎随着厚度的增加而增加,然后在厚度超过约1微米时迅速降低。认为该效应与蒸发过程中蒸发的CdSe装料组成的变化有关。在200摄氏度(473 K)的基板温度下沉积的薄膜显示出随着沉积速率增加到大约0.5 nm s $ +,电阻率从低于10 $ + 2 $ /约ega m迅速增加到高于1约ega m。 $ MIN @ 1 $ /,而对于高于该值和高达3 nm的速率s $ + $ MIN @ 1 $ /,电阻率基本上保持恒定。据认为,这种行为与分别由于增加的晶粒边界散射和俘获效应而导致的迁移率和/或自由载流子浓度的降低有关,这是由于平均晶粒尺寸随沉积速率的增加而减小的结果。电阻率在很大程度上取决于沉积过程中的基板温度,随着温度的升高而升高,直至约75摄氏度(约等于350 K),电阻率会适度增加,随后迅速升高,通常为三十年,直至100摄氏度(373 K)。 ),高于该值则稳定在基本恒定的值上。先前的工作已将较低电阻率的CdSe膜的起源确定为Cd离子过多的结果,而化学计量膜通常具有较高的电阻率。本结果表明,超过100摄氏度(约等于400K)的衬底温度对于化学计量膜的沉积是必需的。由于预期的电导率被热激活,电阻率随温度升高而降低。在200摄氏度(473 K)的基板温度下制备的样品在较低和较高的温度下分别显示出约0.02 eV和0.14 eV的活化能。低温行为与通过跳变机制的传导相一致,而后者则适合由Petritz提出并先前在CdS薄膜中观察到的跨晶间势垒的热激发。 !25

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