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Etch Process Technology for High Density STT-MRAM.

机译:蚀刻工艺技术高密度STT-MRAM。

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Summary form only given. In information and communication technology (ICT) equipment indispensable for modern society, semiconductor memories occupy the main position of storage memories, working memories, and e-memories in logic blocks. In current semiconductor memories, rapid increase in the power consumption is most serious issue, as the more energy-saving is strongly required for ICT technology. From above view point, STT-MRAM and its application such as NV-Logic are aggressively studied in the world and many excellent results were published. However, almost results of STT-MRAM were fabricated by ion beam etch (IBE) process. Therefore, for higher density STT-MRAM's mass-production under wide patterning process margin and high TAT, plasma based reactive ion etch (RIE) process technology for MTJs is needed. In this invited paper, it is reviewed our previas results regarding STT-MRAM and NV-Logic fabricated by RIE process as shown in Fig. 1. It is shown that STT-MRAM and NV-MCU etc. were successfully worked under extremely low power consumption. Moreover, it is reviewed our previas results of RIE process technology itself. We presented process and device results from a developed chemistry set which significantly reduces the etch damage compared with conventional chemistry. An etched MTJ stack profile is included in Fig. 2. The damage caused by RIE on the magnetic properties of the CoFeB free layer in a MTJ with a perpendicular easy axis (p-MTJ), and on the TMR ratio of CoFeB-MgO p-MTJs was characterized to identify its root cause. Fig. 3 includes TMR data from a selection of different chemistry sets. Our developed chemistry is based on learning that it is N and H radicals that are the primary source of damage. With our developed process, high TMR ratio was achieved with very slight degradation. We report our chemistry, its underlying concept, resultant MTJ profiles, device electrical and magnetic properties. Finally, we summarize the MTJ damage mechanism useful for bringing MTJ fabrication etch technology to maturity.
机译:摘要表格仅给出。在信息和通信技术(ICT)设备对于现代社会不可或缺的设备中,半导体存储器占据逻辑块中存储存储器,工作记忆和电子存储器的主要位置。在目前的半导体存储器中,功耗的快速增长是最严重的问题,因为ICT技术强烈需要更高的节能。从以上观点来看,在世界上积极研究了STT-MRAM及其如NV-Logic的应用,并且许多出色的结果出版了许多优秀的结果。然而,通过离子束蚀刻(IBE)工艺制造了STT-MRAM的几乎结果。因此,对于在宽的图案化过程边缘下的高密度STT-MRAM的批量生产,因此需要用于MTJ的基于等离子体的反应离子蚀刻(RIE)工艺技术。在此邀请纸中,审查了关于由RIE过程制造的STT-MRAM和NV逻辑的预测结果,如图1所示。显示STT-MRAM和NV-MCU等在极低的功率下成功地工作消耗。此外,它审查了RIE过程技术本身的预期结果。我们介绍了开发的化学集的过程和装置,与常规化学相比,显着降低了蚀刻损伤。蚀刻的MTJ堆叠轮廓包括在图2中。由RIE在MTJ中的COFEB自由层的磁性造成的损伤,垂直易轴(P-MTJ)以及CoFeB-MgO P的TMR比率-MTJS的特征是识别其根本原因。图3包括来自各种不同化学集的TMR数据。我们发达的化学基于学习,它是N和H激进的主要损坏源。随着我们发达的过程,通过非常轻微的降解实现了高TMR比率。我们报告了我们的化学,其潜在的概念,结果MTJ型材,装置电气和磁性。最后,我们总结了用于将MTJ制造蚀刻技术带来成熟的MTJ损伤机制。

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