Characterization of Clean after Photoresist Removal from Wafers with Copper Pillars with Lead-Free Solder Caps

摘要

Opportunities for developing enabling packaging schemes are being pursued as part of device improvement strategies for electronic products. Processes such as embedded technologies in wafer level packaging and 3-D chip architecture schemes open up opportunities for realization of a variety of package configurations. As a result, there are many opportunities to impact both device performance and the processes used to create them. In the area of electroplated solder applications, there has been widespread adoption of copper pillar bumps with lead free solder caps. As more data is gathered using this process, one area of growing interest is the characterization of polymer photoresist residue on the side walls of plated copper pillars with lead-free solder caps. As has been seen with other processes, cleaning challenges have increased in tighter pitch applications. This paper will describe wet cleaning processes used today for copper pillar cleans, with special focus on characterization of the Cu pillar and solder side walls. Examples using several different photoresists and copper and solder configurations will be examined. Samples with differing copper/solder bump heights and pitches will be discussed. Cleaning and compatibility results will be shown.