A DEVS-based Modeling and Behavioral Fault Simulator for RT-Level Digital Circuits

摘要

The domain of fault simulation for digital circuits described at the RT-level is currently under heavy researches. The goal of these researches is to define a fast and efficient methodology for the validation of test patterns very early in the design flow. We propose in this article a new approach for the modeling and the simulation of behavioral faults for digital circuits described in the VHDL language, using a discrete event approach. This methodology, based on the DEVS formalism, is implemented in a working prototype, and experimental results show the correctness of our approach and the efficiency of our behavioral fault simulator called BFS-DEVS. The fault model used to validate our results is essentially based on the stuck-at fault model since a good simple stuck-at faults coverage rate implies a good real faults coverage rate.