In this paper, a high-frequency CMOS charge pump is designed using T-spice simulation tools, i.e., s edit, 1 edit, and t edit tools for PLL-based applications at 130-nm technology. The simple and symmetric structure of the circuit reduces serious problems such as spur tones and jitter noises which occur in traditional charge pump circuits and provides more stable operation under a 1-V power supply with the use of error amplifier. Pull-up and pull-down currents are kept to 3 μA and are operated at an operating frequency of 1 GHz.
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