Test Generation for Open and Delay Faults in CMOS Circuits

摘要

This paper proposes a novel circuit transformation based method to generate tests for cross-wire open, transistor stuck-open and delay faults inside CMOS cells/gates as well as transition faults in interconnects between gates using a unified model, called dynamic aggressor-victim type of bridging fault model (DBF). The unified fault model allows handling all these faults in one ATPG run and thus the total test generation time can be reduced and very compact (small) test sets can be obtained. In addition, we present a path-based test generation method that aims to choose the smallest set of paths to cover all faults and each path tends to have the largest delay in the CMOS cell containing it. Using this method one can generate tests with better quality without increasing the number of test patterns. Experimental results show that on average 1.28X (1.35X) of the number of test patterns for transition delay faults are sufficient to detect all open and delay faults in CMOS cells as well as the transition faults in gate interconnects of ISCAS'89 (IWLS'05) circuits.