A quick jitter tolerance estimation technique for bang-bang CDRs

摘要

Simulating/Measuring the jitter tolerance of clock and data recovery (CDR) circuits, and confirming if the associated jitter tolerance meets the required specification for a specified communication standard, is an important consideration for designing/testing high-speed serial link interface circuits. However, conducting such performance evaluations are costly and time-consuming. In this paper, a simple but effective testing method for evaluating the tracking capability of bang-bang CDR circuits is introduced. The tracking capability of the CDR loop is obtained by simply inverting the recovered clock to produce a 0.5 unit interval (UI) phase shift and capture the tracking time. The proposed technique is easily implemented, because of its fully-digital characteristic, and suitable for testing CDRs that is embedded in a complex interface transceiver. Then, a quick jitter tolerance estimation technique based on the obtained tracking capability is proposed to simplify the time-consuming process as well as avoid the costly test equipment required for designing and/or testing CDR circuits. Experimental results show that the proposed techniques could precisely evaluate the tracking capability and efficiently reduce test costs in acquiring complete jitter tolerance testing.