A CDR CIRCUIT HAVING IMPROVED JITTER CHARACTERISTICS BY USING A BANG-BANG PHASE DETECTOR

摘要

PURPOSE: A clock data recovery circuit having an improved jitter character using a bang-bang phase detector is provided to improve effectiveness using a bang-bang phase detector having an improved jitter character. CONSTITUTION: A bang-bang phase detector comprises an edge detector for detecting edges from input data and a decision circuit connected to the output end of the edge detector. The decision circuit determines advance or lag state of a clock compared with the input data. The edge detector comprises 2 flip-flops and an AND gate. The flip-flops maintain first stable state before input for determining the second stable state. The decision circuit comprises two latches registered in the time for registering a resistor, a counter, and digital information on a data signal bus on disable time.