Simulation and Hardware Implementation of Interleaved SEPIC Converter with Valley-Fill Circuit for HBLED System

摘要

LED lamps are nowadays preferred for lighting compared to the fluorescent lamps due to its longer lifetime and low power consumption. But the design of driver circuits designed for high brightness (HB) LED demands high power factor, more reliability, high efficiency and precise control. Therefore, to achieve this, a single-stage power factor correction model (PFC) and valley-fill is proposed in this paper. Valley-fill incorporated in SEPIC reduces the strain on output diode and middle capacitor, thus achieving great power factor and competence. Further to moderate the ripple at input and output stages, an interleaving concept is applied to SEPIC with valley-fill circuit. The combination of interleaving and valley-fill circuit leads to reduced voltage ripple, improved power factor and efficiency. A simulation study of the proposed SEPIC converter is carried out by MATLAB/SIMULINK. The performance factors such as source power factor, supply THD, supply distortion factor, supply displacement factor, power loss, output voltage ripple and efficiency are computed, and the results are compared with the classical SEPIC converter without valley-fill circuit. A prototype of an interleaved SEPIC converter is assembled to confirm the simulation results.