Optimized design and performance analysis of Johnson counter using 45 nm technology

摘要

Sequential circuits largely contribute to the power dissipation and propagation delay in a digital system. Low power, less delay and area efficient sequential circuit design has been the major concern for VLSI designers. The selection of optimized design technology plays a key role in achieving the above parameters. A counter is a sequential circuit having wide application area in microcontroller circuits including PLL, Digital to Analog converters, signal generators, signal synthesizers etc. In this paper a low power, high speed and cost efficient 4 bit Johnson counter is proposed. Deployed flip flop circuit uses 14 transistors to realize the negative edge triggered master slave D flip flop operation. Performance and cost of the proposed counter is compared against the conventional counter. The proposed design is found 48.86 % faster with having 43.22 % lesser power dissipation than conventional design. The transistor requirements in the proposed counter is also 69.5 % lesser making it an optimized design in terms of area.