机译:采用45 nm体CMOS技术的栅极硅化ESD NMOSFET的设计优化
Infineon Technologies, Am Campeon, 85579, Neubiberg, Germany;
IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA;
Infineon Technologies, Am Campeon, 85579, Neubiberg, Germany;
IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA;
IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA;
IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA;
Infineon Technologies, Am Campeon, 85579, Neubiberg, Germany;
IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA;
IBM, Semiconductor Research Center, Essex Junction, VT 05452, USA;
机译:带有ESD注入的65nm体CMOS ESD NMOSFET的ESD失效机理分析
机译:热载流子对45和65 nm CMOS技术中nMOSFET可变性的影响
机译:采用BIMOS合并的双背对背SCR的混合体28nm FD-SOI先进CMOS技术实现超紧凑ESD保护
机译:45nm散装CMOS技术中门硅硅酸炉ESD NMOSFET的设计优化
机译:45 nm CMOS锁相环中组件的设计和优化。
机译:用于亚微米像素的45 nm堆叠式CMOS图像传感器处理技术
机译:使用45nm技术优化CMOS设计完整加法器
机译:批量CmOs VLsI技术研究。第1部分:可扩展CmOs设计规则。第2部分pLa(可编程逻辑阵列)设计的CmOs方法