An Effective Approach Based on Partial Duplication for Reducing Soft Error Rate in SRAM-Based FPGA

摘要

In this paper, we present an effective approach for reducing soft error rate (SER) in SRAM-based FPGA. First, the entire system is divided into several modules according to its function. Then the soft error rate of each module is calculated by an analytical estimation method. Finally, rather than performing mitigation for all the modules in the system to achieve high reliability, the modules with highest soft error rate have a priority to be mitigated, i.e. we perform mitigation for the entire system based on partial duplication. Experimental results verify our proposed method.