An Energy-Efficient 32-bit Kogge-Stone Adder Using a Dual-Phase Partially-Adiabatic Logic Family

摘要

This paper describes the implementation of an energy-efficient 32-bit Kogge-Stone Adder (KSA) using a proposed dual-phase partially-adiabatic logic family. The energy efficiency of the proposed implementation was compared to a CMOS and a few other adiabatic implementations and it was found that the proposed implementation is up to 79% more energy efficient than a CMOS implementation (at 1MHz) and 22% more energy-efficient than the next best adiabatic implementation (2N-2N2P KSA at 10MHz). The low energy operation of the proposed implementation makes the adder suitable for use in larger designs.