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Power gating techniques on Platform Controller Hub

机译:平台控制器集线器上的功率门控技术

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Energy efficiency has long been a first-order goal for mobile devices such as cell phones to extend battery life. In the last decade, effective energy use has also become a focus for larger computing devices for several reasons; namely expansion of mobile computing and data centers. Customers require maximum battery life from notebooks, netbooks, and tablets. Achieving optimal battery performance requires careful management of energy consumption. This paper describes the power gating techniques which has achieved ∼1000mW of effective power savings on Platform Controller Hub (PCH) and is proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, to make power savings possible without performance trade-off, many design considerations combining architecture, floorplanning, innovative hardware design and software configurations are required. This paper presents the power gating strategies starting from early design planning to post silicon validation correlation methodology considering: 1) silicon floorplan partitioning into multiple power domains 2) stages of PFET switches assignment 3) The trade-off between a wake-up overhead and leakage savings design 4) the complete definition of power gate/ungate power sequence from partition level to system level 5) PDN noise analysis and leveraging of “zero-cost” noise mitigation techniques to address the various possible worst case power noise droop events cause by power gate/ungate activities. These power gating strategies are consider successful, when not only the desired power target is achieved; but a smooth transition of power state from sleep mode to full power mode and vice versa, is achieved without system hang or performance corruption. The paper is concluded with post silicon validation results correlated to selected individual power partition's gate/ungate activity; which is controlled by a specially customized test script to examine the pow- - er fet's gating/ungating functionality v.s. design expectation.
机译:能源效率一直是移动设备如手机,以延长电池寿命的一阶目标。在过去的十年中,有效的能源利用也已成为一个重点有以下几个原因更大的计算设备;即膨胀的移动计算和数据中心。客户需要从笔记本电脑,上网本和平板电脑最长的电池寿命。实现最佳的电池性能要求的能源消耗的精心管理。本文描述了功率门控其对平台控制器集线器(PCH)来实现的有效功率节省~1000mW和被证明是用于保持移动计算能力和电池寿命延长一个好策略的技术。然而,为了使节能成为可能不表现权衡,许多设计上的考虑相结合的建筑,平面规划,需要创新性的硬件设计和软件配置。本文介绍了功率门控,从早期的设计规划后硅验证的相关方法考虑启动策略:1)硅平面布置图划分成多个电源域2)PFET的阶段切换分配3)唤醒开销和泄漏之间的权衡节省设计4)从划分级别到系统级5)PDN噪声分析功率门/ ungate功率序列的完整定义,并利用“零成本”的噪声抑制技术,以解决各种可能的最坏情况下的功率噪声下垂事件由电源引起栅/ ungate活动。这些电源门控策略是考虑成功的时候,不仅所需的功率目标得以实现;但电源状态从休眠模式到全功率模式和副平稳过渡反之亦然,而没有系统挂起或性能腐败实现。纸张被结束了与关联于所选择的各个功率分区的栅/ ungate活性交硅验证结果;它是由专门定制的测试脚本控制的检查影响声 - 呃FET的浇注系统/ ungating功能V.S.设计预期。

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