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Power gating techniques on Platform Controller Hub

机译:Platform Controller Hub上的电源门控技术

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Energy efficiency has long been a first-order goal for mobile devices such as cell phones to extend battery life. In the last decade, effective energy use has also become a focus for larger computing devices for several reasons; namely expansion of mobile computing and data centers. Customers require maximum battery life from notebooks, netbooks, and tablets. Achieving optimal battery performance requires careful management of energy consumption. This paper describes the power gating techniques which has achieved ∼1000mW of effective power savings on Platform Controller Hub (PCH) and is proven to be a good strategy for preserving mobile computing power and extension of battery life span. However, to make power savings possible without performance trade-off, many design considerations combining architecture, floorplanning, innovative hardware design and software configurations are required. This paper presents the power gating strategies starting from early design planning to post silicon validation correlation methodology considering: 1) silicon floorplan partitioning into multiple power domains 2) stages of PFET switches assignment 3) The trade-off between a wake-up overhead and leakage savings design 4) the complete definition of power gate/ungate power sequence from partition level to system level 5) PDN noise analysis and leveraging of “zero-cost” noise mitigation techniques to address the various possible worst case power noise droop events cause by power gate/ungate activities. These power gating strategies are consider successful, when not only the desired power target is achieved; but a smooth transition of power state from sleep mode to full power mode and vice versa, is achieved without system hang or performance corruption. The paper is concluded with post silicon validation results correlated to selected individual power partition''s gate/ungate activity; which is controlled by a specially customized test script to examine the pow--er fet''s gating/ungating functionality v.s. design expectation.
机译:长期以来,提高能效一直是手机等移动设备延长电池寿命的首要目标。在过去的十年中,由于多种原因,有效的能源使用也成为大型计算设备的关注焦点。即扩展移动计算和数据中心。客户要求笔记本电脑,上网本和平板电脑的电池寿命最大化。要获得最佳的电池性能,需要对能耗进行仔细管理。本文介绍了功率门控技术,该技术已在Platform Controller Hub(PCH)上实现了约1000mW的有效功率节省,并被证明是保留移动计算能力和延长电池寿命的良好策略。但是,为了在不牺牲性能的前提下节省功率,需要综合考虑架构,布局规划,创新的硬件设计和软件配置的许多设计注意事项。本文介绍了从早期设计规划到后期硅验证相关方法论的电源门控策略,其中包括:1)硅平面图划分为多个电源域2)PFET开关分配阶段3)唤醒开销与泄漏之间的权衡节约设计4)完整定义从分区级别到系统级别的功率门/非门功率序列5)PDN噪声分析,并利用“零成本”噪声缓解技术来解决由功率引起的各种可能的最坏情况下的功率噪声下垂事件登机门/ ungate活动。当不仅实现了所需的功率目标时,这些功率门控策略也被认为是成功的。但可以实现电源状态从睡眠模式到全功率模式的平滑过渡,反之亦然,而不会导致系统挂起或性能下降。本文的结论是硅后验证结果与选定的各个功率分区的栅极/栅极活动有关。由专门定制的测试脚本控制,以检查电源- -- er fet的门控/非门控功能设计期望。

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