Resist process control for 32-nm logic node and beyondwith NA > 1.30 immersion exposure tool

摘要

Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns,we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logicpatterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrowangle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET isused. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resistpattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annularillumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns,it is necessary to expand the overlapping CD process window. Better process margin is realized through the combinationof hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.