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System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis

机译:特定于应用专用MPSOC互连合成的系统级性能估计

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We present a framework for development of streaming applications as concurrent software modules running on multi-processors system-on-chips (MPSoC). We propose an iterative design space exploration mechanism to customize MPSoC architecture for given applications. Central to the exploration engine is our system-level performance estimation methodology, that both quickly and accurately determine quality of candidate architectures. We implemented a number of streaming applications on candidate architectures that were emulated on an FPGA. Hardware measurements show that our system-level performance estimation method incurs only 15% error in predicting application throughput. More importantly, it always correctly guides design space exploration by achieving 100% fidelity in quality-ranking candidate architectures. Compared to behavioral simulation of compiled code, our system-level estimator runs more than 12 times faster, and requires 7 times less memory.
机译:我们提出了一种开发流应用的框架,作为在多处理器系统上运行的并发软件模块(MPSOC)。我们提出了一种迭代设计空间探索机制,用于定制棉掌架构,以便给定应用程序。勘探引擎的核心是我们的系统级性能估计方法,即快速准确地确定候选架构的质量。我们在FPGA上实现了许多关于候选体系结构的流型应用程序。硬件测量表明,我们的系统级性能估计方法仅在预测应用程序吞吐量中引起15%的错误。更重要的是,它始终通过在质量排名的候选架构中实现100%的保真度来正确地指导设计空间探索。与编译代码的行为模拟相比,我们的系统级估计器速度快12倍以上,内存少7倍。

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