The performance of implant-free (IF), n-type III-V MOSFETs with an In0.75Ga0.25As channel have been evaluated using a 2D finite-element Monte Carlo device simulator. We investigate the device performance of a set of scaled transistors with gate lengths of 30, 20 and 15 nm at a drain bias of 0.5 V to determine whether this novel architecture can deliver high drain current at low bias conditions required for high-performance CMOS applications.
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机译：使用IN 0.75 GA 0.25>作为通道的无植入式（IF），N型III-V MOSFET的性能已经使用2D有限元蒙特卡洛评估设备模拟器。我们研究了一组缩放晶体管的装置性能，栅极长度为30,20和15nm，漏极偏置为0.5V以确定该新颖架构是否可以在高性能CMOS应用所需的低偏置条件下提供高漏极电流。
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