32nm design rule and process exploration flow

摘要

Semiconductor manufacturers spend hundreds of millions of dollars and years of development time to create a newmanufacturing process and to design frontrunner products to work on the new process. A considerable percentage of thislarge investment is aimed at producing the process design rules and related lithography technology to pattern the newproducts successfully. Significant additional cost and time is needed in both process and design development if thedesign rules or lithography strategy must be modified. Therefore, early and accurate prediction of both process designrules and lithography options is necessary for minimizing cost and timing in semiconductor development. This paper describes a methodology to determine the optimum design rules and lithography conditions with highaccuracy early in the development lifecycle. We present results from the 32nm logic node but the methodology can beextended to the 22nm node or any other node. This work involves: automated generation of extended realistic logic testlayouts utilizing programmed teststructures for a variety of design rules; determining a range of optical illumination andprocess conditions to test for each critical design layer; using these illumination conditions to create a extrapolatableprocess window OPC model which is matched to rigorous TCAD lithography focus-exposure full chemically amplifiedresist models; creating reticle enhancement technique (RET) recipes which are flexible enough to be used over a varietyof design rule and illumination conditions; OPC recipes which are flexible enough to be used over a variety of designrule and illumination conditions; and OPC verification to find, categorize and report all patterning issues found in thedifferent design and illumination variations. In this work we describe in detail the individual steps in the methodology,and provide results of its use for 32nm node design rule and process optimization.