Technology Interactions on Reticle Delivery

摘要

Reticle cost and cycle time to deliver new circuit designs to a wafer fab remain key focus areas for advancedsemiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximitycorrection as applied to critical layers have increased the burden on mask data preparation and reticle writing steps of themask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticlein the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelengthexposure in extremely low k, lithography exacerbates the underlying trends. Two important factors come together to drive the economics and performance of the reticle line: the complexity of thedesigns and the productivity of e-beam writing tools. The designs, OPC methods, and writing tool capabilities continueto evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexityacross 90nm, 65nm, and 45nm logic designs using the gate and metal-I critical layers. The writing tool throughputtesting uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrarydesigns. Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capabilityby introducing new quantitative methods, benchmarking metrics, and testing strategies. The findings are projected intothe future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, orpossible gaps in technology development.