Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

摘要

Split gate flash memory architecture has gained a strong foothold in the embedded nonvolatile memory due to its over-erase immunity, enhanced array efficiency, and low power operation [1]. Furthermore, the silicon nanocrystal based split gate memory has been considered as one of the most promising technologies due to its ability to scale beyond 90nm [2, 3]. However, in order for the silicon nanocrystal memory to replace the conventional floating gate technology, it needs to demonstrate sufficient operating window throughout its lifetime and also meet reliability requirements such as endurance and long term data retention [4]. We have systematically evaluated the effect of nanocrystal size on long-term reliability. In this paper, we present the performance characteristics of such a silicon nanocrystal split gate bitcell and report an optimal bitcell process and integration scheme for memory arrays.