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An Automated Design Flow for NoC-based MPSoCs on FPGA

机译:基于NOC的基于MPSoC的自动化设计流程

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Increased dynamics of the embedded devices market makes reduced time-to-market emerge as one of most challenging tasks in modern embedded system design. The complexity of Multiprocessor Systems-on-Chip (MPSoCs) rapidly increases and Networks-on-Chips (NoCs) have emerged as design strategy to cope with it. In order to allow fast generation of these platforms in the development phase, a full design flow is required. On the other hand, modern FPGAs provide the possibility for fast and low-cost prototyping, representing an efficient response to these needs. In this paper we present a framework, based on the Xilinx Embedded Development Kit (EDK) design flow, for the generation of MPSoCs based on NoCs. The tool provides system designers with the possibility to easily and quickly generate desired architectures that can be helpful for testing, debugging and verifying purposes. Our integrated design flow takes as input a textual description of the system and produces as final result a configuration bitstream file. The framework has been tested and verified on a Xilinx Virtex-II Pro board.
机译:嵌入式设备市场的动态增加使得市场减少,作为现代嵌入式系统设计中最具挑战性的任务之一。多处理器系统上片上的复杂性(MPSOCs)迅速增加,芯片(NOCS)被出现为应对它的设计策略。为了允许在开发阶段进行快速生成这些平台,需要完整的设计流程。另一方面,现代FPGA提供了快速和低成本的原型设计的可能性,代表了对这些需求的有效响应。在本文中,我们介绍了一个框架,基于Xilinx嵌入式开发套件(EDK)设计流程,用于基于NOC的MPSoC。该工具提供系统设计人员,可以轻松快速地生成可能有助于测试,调试和验证目的的所需架构。我们的集成设计流程为输入系统的文本描述,并以最终结果产生配置比特流文件。该框架已经过测试并验证了Xilinx Virtex-II Pro主板。

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