Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?

摘要

As the fabrication process technology is moving from submicron region to deep submicron or nanometer region, the impact of process parameter variations are becoming more and more dominant, increasing the loss in yield due to variations in leakage power and delay. As a consequence, parametric yield loss has become a serious concern of the fabrication houses. This has opened up a challenge to the designers' community to design circuits that are tolerant to process parameter variations, thereby increasing the parametric yield. In this paper we have studied the impact of process parameter variations on the representative static approaches of runtime leakage power reduction and compared them with a proposed approach using Monte-Carlo simulation. The simulation results indicate that the proposed approach provides higher parametric yield compared to the existing representative approaches with comparable reduction in total and leakage power.