Soaring distortions for immersion lithography with 193nm wavelength has necessiated the Next Generation Lithography (NGLs) such as Electron Beam Lithography (EBL). While single e-beam lithography suffers from very low throughput, Multiple Electron Beam Lithography (MEBL) improves it by writing with multiple e-beams in parallel, each dedicated to a disjoint region called a vertical stripe. However, layout patterns, in particular routing segments, vias and short polygons crossing over stripe boundary (stitch line) causes severe pattern distortion leading to malfunctioning of the chip. We minimize these stitch unfriendly patterns at post-layout stage based on perturbation of wire segments by formulating it as a maximum matching problem. Experimental results comprise two variants of perturbations of wire segments. Each variant shows significant minimization of stitch unfriendly patterns, thereby making an already optimized design more MEBL friendly without increasing the wirelength.
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