Behavioral synthesis entails application of a sequence of transformations to compile a high-level description of a hardware design (e.g., in C/C++/SystemC) into a Register-Transfer Level (RTL) implementation. We present a scalable equivalence checking framework to validate the correctness of compiler transformations employed by behavioral synthesis. Our approach is based on dual-rail symbolic simulation of the input and output design representations of a transformation. We have evaluated our framework on transformations applied to several designs by an open source behavioral synthesis tool, and we present initial results demonstrating the approach.
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机译：行为合成需要一系列转换序列，以将硬件设计的高级描述（例如，在C / C ++ / Systemc）中编译成寄存器传输级别（RTL）实现。我们呈现可扩展的等价检查框架，以验证行为合成所采用的编译器变换的正确性。我们的方法是基于转换输入和输出设计表示的双轨符号模拟。我们已经通过开源行为综合工具评估了对应用于多个设计的转换框架，并且我们呈现了展示方法的初始结果。
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