Modern processors face growing verification and reliability challenges posed by increasing micro-architecture complexity and aggressive technology scaling. While viable approaches have been proposed to address these challenges in the context of uniprocessors, little work has been done for emerging multithreaded processors. Multithreading raises new issues for validation due to inter-thread interactions and inherent complexity of the underlying hardware. We propose an extension of the DIVA approach [1], which employs a simple checker processor to effectively validate the complex superscalar processor, to perform instruction-level runtime validation for both intra-thread and inter-thread correctness properties for multithreaded execution. We present the validation methodology using a representative simultaneous-multithreaded (SMT) architecture, and briefly discuss its general applicability to other forms of multithreading. Detailed timing simulation shows this solution has low performance penalty, while providing general robustness against both operational and functional errors with relatively small hardware overhead.
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