CHARGE TRAPPING – A MAJOR RELIABILITY CHALLENGE FOR HIGH-K GATE DIELECTRICS

摘要

This paper focuses on a major reliability issue for Hf-based high-k gate dielectrics. It will show that (1) the operating lifetime extracted from the trapping induced threshold voltage shift, ΔV_(th), is much shorter than that extracted from Time-Dependent Dielectric Breakdown, and therefore the actual device lifetime is limited by charge trapping; (2) Biased in inversion, electron trapping is the dominant mechanism for nMOSFETs; hole trapping is the dominant mechanism for pMOSFETs at low voltages (< 2 eV); (3) for pMOSFETs biased at high voltages (> 2.6 V), either net electron trapping or net hole trapping are observed, depending on the details of the stress conditions; (4) the above can be explained by the electron and hole currents through the dielectric for a given stress condition; (5) electron traps (with the energy level at ~0.68eV below E_c of the dielectric) give rise to Frenkel-Poole (F-P) conduction; (6) hole traps do not participate in F-P conduction in the temperature range studied (300-500 k).