Relaxation Induced Excess Leakage Current in Recessed Si_(1-x)Ge_x Source/Drain Junctions

摘要

This paper presents an investigation of the effect of the relaxation induced defects on the electrical performance of recessed Si_(1-x)Ge_x source/drain junctions. It is shown, that the peripheral leakage current density scales exponentially with the total epilayer thickness, which allows the estimation of the characteristic length in good agreement with previously published values. In addition, the area leakage current density shows for relaxed Si_(0.7)Ge_(0.3) recessed S/D junctions an exponential increase with the position of the epi interface with respect to the junction. For strained Si_(0.8)Ge_(0.2) recessed S/D junctions, an unusual dependence of the area leakage current density on the etch depth is revealed in this work. At the same time, for 48 nm etch depth, the leakage current components are not monotonically increasing with the Ge content. This could point to a size effect of the active areas, affecting the strain relaxation in the SiGe layers and the tensile strain in the underlying silicon substrate.