HIGH-K MATERIALS FOR TUNNEL BARRIER ENGINEERING IN FUTURE MEMORY TECHNOLOGIES

摘要

Replacing the tunnel oxide or interpoly oxide of a floating gate Flash memory cell by an engineered tunneling barrier allows lowering the voltage necessary to program or erase the memory cell. We use dual layer dielectric stacks with different dielectric constant, allowing a high tunneling current at relatively low applied voltage while providing good data retention. Stacks consisting of SiO_2 and HfO2 or Al2O3 have been studied in single poly memory cells, demonstrating low voltage programming by tunneling and 10 years of data retention. A SiCV HfO2 stack has been integrated in a 0.18μm HIMOS? process for low voltage erasing by tunneling through the interpoly dielectric.