In this paper, the novel Quasi-SOI CMOS architecture is fabricated based on bulk Si substrate for the first time. The whole fabrication is basically compatible with the conventional CMOS technology. The path of the drain-induced barrier lowering (DIBL) effect can be effectively suppressed by the "L-Type" insulator surrounding the source and drain in Quasi-SOI MOSFET. Such device structure can effectively suppress the short-channel effects (SCEs) and prevent the transistor from the bulk punch-through. The leakage current will not increase with the high doping concentration ofihe-substrate due to the absence of P/N junctions surrounding the S/D regions which brings more flexibility on the modulation of the threshold voltage. Moreover, the influence of process-induced variations on the new transistor perfqrmance and implications for manufacturing processes comparing with UTB SOI MOSFET are also studied by simulations in order to investigate the sensitivity of the important characteristics to the device crucial physical parameter fluctuations introduced by the process. The results show that Quasi-SOI MOSFET can be more tolerant of process-induced variation for the deep nanometer scale regime. The highly manufacturable Quasi-SOI MOSFET which can combine the advantages of ultra-thin body (UTB) SOI MOSFET and bulk silicon device can be considered as a promising candidate for highly scaled devices.
展开▼
