LIMITATIONS OF CMOS SCALING: WHAT'S NEXT?

摘要

Fundamental barriers to the continued scaling of high performance CMOS have motivated interest in new device structures and materials. Partially-depleted SOI has extended VLSI performance, but with some additional design complexity. Fully-depleted SOI is a possible scaled successor to this structure. Power consumption and cooling capability have emerged as first order constraints in next-generation processors. Gate dielectric tunneling, device self heating, and radiation-induced single-event upsets present new device and circuit design challenges, requiring new materials, such as strained silicon and high-permittivity gate dielectric, in order to enable continued improvements in the deep sub-100 nm regime.