Low-voltage Scaling Limitations For Nano-scale Cmos Lsis

摘要

The minimum operating voltage (V_(min)) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V_(min), which is governed by SRAM cells, rapidly increases as devices are miniaturized due to the ever-larger variations in the threshold voltage (V_T) of MOSFETs. The V_(min), however, is reduced to the sub-l-V region by using repair techniques and new MOSFETs (e.g., FD-SOls and/or high-k metal gates) that can reduce V_T variations.