CMOS SCALING AND NANOELECTRONICS NEW MATERIALS AND PROCESSES

摘要

Silicon based integrated circuits technology has demonstrated a capability cc keep bringing down the minimum geometry in the past three and a half decades, and made tremendous contributions to the modern society in terms of computing and communication capability accessible for every body and made it ubiquitous. In addition, CMOS geometry scaling down has made consecutive reduction of cost per function, i.e. cost per memory bit and cost per logic gate driven down by a factor of as much as 30-50% in every technology node, which in conjunction with increased density and performance improvement by 100% and 30-50%, respectively, allowed silicon based CMOS staying at the main stage of integrated circuits. However, as the minimum geometry approaches below sub 50nm ranges, there are a variety of bottlenecks showing up as pointed out on the ITRS technology road map. (1) This report describes those bottle necks and recent investigations for possible solutions, followed by suggesting change directions to avoid crash course into the red brick walls.