Hardware Aware eIRA LDPC Code Generation

摘要

This paper presents a new methodology for generating eIRA LDPC codes with low hardware cost. Approach is based on hierarchical matrices and primitive generators. Apart from implementation considerations, proposed method shows good BER performance due to a pseudo-random construction and the absence of length-four cycles. Moreover, low-weight codewords and near-codewords are also considered in order to reduce error floors.